To view the corresponding available BSDL models for Designer v9.0 SP2A released on 9/1/2010, please choose one of the following FPGA families:
Low-Power FPGAs
Mixed-Signal FPGA
RadTolerant
Antifuse
Legacy & Discontinued Devices
ACT 1 / ACT 2 / ACT 3 / 1200XL: The BSDL for these devices are not available as these families do not support JTAG Boundary Scan.
For more information, please review the Actel
BSDL Files Format Description application note.
Notes
- The BSDL files contained herein are Generic BSDL only. The Actel
Designer software currently supports the exporting of Design-Specific
BSDL for the IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, ProASIC3L, SmartFusion, Fusion, SX-A, eX, SX, RTAX-S/SL, RT ProASIC3, RTSX-S, RTSX, ProASICPLUS, and ProASIC families.
- While doing boundary scan testing of a programmed device, the I/Os are defined per design (use design-specific BSDL). I/Os of an unprogrammed device have default state: LVTTL 3.3 V, lowest drive strength, slow slew, and weak pull-up enabled (where applicable). This default state can be overridden by IOCONFIG instruction.
- All BSDL files are syntax checked using Agilent Technologies syntax
checker tool.
