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Datasheets

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User's Guides and Manuals

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Application Notes

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  AC163: Axcelerator Carry-Connect Macros App Note  PDF 118 KB 1/2003
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  AC164: Axcelerator Family Memory Blocks App Note  PDF 151 KB 1/2003
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  AC170: Prototyping RTAX-S Using Axcelerator Devices App Note  PDF 131 KB 4/2003
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  AC173: Differences Between RTAX-S/SL and Axcelerator App Note  PDF 62 KB 5/2003
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  AC175: Axcelerator Family PLL and Clock Management App Note  PDF 174 KB 6/2003
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  AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note  PDF 186 KB 7/2003
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  AC182: Axcelerator I/O Selection Guide App Note  PDF 362 KB 8/2003
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  AC183: Using Global Resources in Actel's Axcelerator Family App Note  PDF 123 KB 8/2003
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  AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note  PDF 148 KB 8/2003
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  AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note  PDF 708 KB 3/2012
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  AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment App Note  PDF 80 KB 5/2004
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  AC209: Axcelerator Family Footprint Compatibility App Note  PDF 44 KB 7/2004
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  AC210: Laser Range Finder Using Actel’s Axcelerator FPGA App Note  PDF 1 MB 7/2004
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  AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note  PDF 642 KB 7/2004
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  AC212: Designing a SuperClock with an Axcelerator Device App Note  PDF 409 KB 9/2004
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  AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note  PDF 232 KB 2/2005
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  AC218: Using Axcelerator RAM as Multipliers App Note  PDF 381 KB 2/2005
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  AC225: Programming Antifuse Devices App Note  PDF 678 KB 11/2011
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  AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note  PDF 713 KB 8/2005
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  AC249: I/O Features in Axcelerator Family Devices App Note  PDF 1 MB 1/2006
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  AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.1 and Older PDF 256 KB 7/2006
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  AC288: Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices App Note  PDF 2 MB 5/2012
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  AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.2 and Newer PDF 691 KB 2/2008
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  AC354: Core8051s Debugging in Axcelerator and RTAX-S Device  PDF 1 MB 10/2011
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  AC373: Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note  PDF 2 MB 11/2011
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  AC379: Advanced Static Timing Analysis Using SmartTime App Note  PDF 6 MB 11/2011
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Product Briefs

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Product Information Brochures (PIB)

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Power Calculator

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