Project Manager
The Libero IDE Project Manager is a true integrated design environment. From design creation through device programming, the IDE design flow window intuitively presents a typical Actel FPGA design flow, where each button on the window is interactive to launch the respective tool when desired. Tooltip context menus display design files, file status, tool version and status, design state, and more.
For the status-conscious designer, Libero IDE indicates pre-simulation, post-simulation, and post-layout design states. Tool buttons clearly indicate status as one of the following:
- White (ready): tool online and source files in place
- Green (finished): process successfully completed
- Red or Gray (problem): tool not online or license issue
A comprehensive file manager displays all design files in the project, appropriately associating each to its proper tool function, such as schematic or HDL source, IP core, stimulus, synthesis, simulation, and Designer implementation files. A Design Hierarchy tab displays a hierarchical representation and structure of the design based on the source files in the project and how they relate to each other. Libero IDE continuously analyzes and updates source files and updates the hierarchy as you move through the project. A dynamically updated log window provides current activity notations and important information. On the right side is the Core Catalog window, which displays and provides access to the wide variety of functional and configurable cores that are available as pre-proven building blocks. The Core Catalog is directly connected to a web repository that is updated regularly by Actel, allowing the designer to access and download the most current versions of the cores. The various cores and building blocks can be dragged and dropped onto the SmartDesign canvas in order to create a complete system-level functional block diagram of the FPGA design.
The Project Manager User Interface
Additional Design Development Tools
