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Introduction to Cortex-M1 is a 1-day class offered at Microsemi's facility in San Jose, CA. The course introduces the Cortex-M1 architecture, instruction set and bus transactions, as well as information on the Cortex-M1 soft core. In addition, the students will use Cortex-M1 development tools such as SmartDesign (Cortex-M1/AMBA system development environment) and SoftConsole. Hands-on lab exercises will allow students to create a CortexM1-based system, simulate the design and complete the design flow though layout.

Course Objectives:

• Understanding basic Cortex-M1 architecture and bus transactions
• Understanding the Cortex-M1 module with a focus on the backend interface
• Functional simulation, synthesis, layout, and timing analysis of the Cortex-M1 soft core
• System usage of the Cortex-M1 soft core

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC tool set

Introduction to Core8051s is a 1-day class offered at Microsemi's facility in San Jose, CA. The course introduces the 8051 architecture and instruction set. In addition, the course provides architectural information on 8051s the highly-configurable 8051 with an AMBA APB interface. The students will be introduced to Core8051s development tools such as SmartDesign (Core8051s/AMBA system development environment) and SoftConsole. Hands-on lab exercises will allow students to create a Core8051s-based system in SmartDesign, simulate the design, and complete the design flow though layout.

Course Objectives:

• Understanding basic 8051 architecture and instruction set
• Understanding the Core8051s modules with a focus on the Core8051s AMBA APB backend interface
• Functional simulation, synthesis, layout, and timing analysis of the Core8051s module
• System usage of the Core8051s module

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Introduction to CoreABC is a 1-day class offered at Microsemi's facility in San Jose, CA. The course introduces the CoreABC processor architecture and instruction set. In addition, the course will introduce CoreABC development tools such as SmartDesign and simulation techniques. Hands-on lab exercises allow students to create a system using CoreABC.

Course Objectives:

• Understanding basic CoreABC architecture and instruction set
• Functional simulation, synthesis, layout, and timing analysis of the CoreABC module
• Building a CoreABC system

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Microsemi Libero SoC training is a 2-day course offered at the Microsemi SoC Product Group headquarters in San Jose, CA. The course consists of lectures and hands-on labs using VHDL or Verilog. Each student will use Libero SoC to take a design from conception to a functioning FPGA targeting the Microsemi SmartFusion silicon.

Course Objectives:

• Project creation with the Libero SoC
• HDL entry using the Libero SoC HDL Editor
• Understanding and using the SmartGen core generator
• Constraining designs and synthesizing with Synplify Pro AE
• Simulation using the ModelSim AE Simulator
• Using the PinEditor and I/O Editor to make pin assignments and set I/O attributes
• Floorplanning with ChipPlanner
• Static timing analysis with SmartTime
• Design layout (place-and-route)
• Generation of back-annotated timing files and programming files
• FPGA programming

Course Requirements:

• Experience with PCs and Windows operating system

This 1-day course is intended for engineers who are using the Microsemi SoftConsole Integrated Development Environment (IDE) to develop applications for the 8051, ARM Cortex-M1, or ARM Cortex-M3 microprocessors embedded in an Microsemi FPGA. Students will learn how to use Microsemi's SoftConsole to develop and debug software applications. Each student will be guided through the complete design flow of a simple design targeting the 8051, ARM Cortex-M1, or ARM Cortex-M3 processor, including debugging the application on a target board. This course is offered at Microsemi's headquarters in San Jose, CA.

Course Objectives:

• SoftConsole Eclipse IDE Overview
• Project creation
• Code development tools
• Source code development and simulation
• Configuring the on-chip debugger
• Debugging applications in a target system

Course Requirements:

• Basic understanding of the 8051, ARM Cortex-M1, or Cortex-M3 architecture
• Familiarity with assembler and C-programming
• Familiarity with on-chip debugging
• Familiarity with the Windows operating system

This course will introduce the Microsemi IGLOO FPGA family as a solution for low power applications. The presentation examines the components of power in an FPGA design, explains how to analyze power consumption using the available Microsemi analysis tools, introduces the power-friendly features of the IGLOO family, and describes techniques to reduce power consumption in designs. This course includes hands-on labs that demonstrate the use of Microsemi's power analysis tools and techniques to improve power consumption. This course is offered at Microsemi's headquarters in San Jose, CA

Course Objectives:

• Understanding of different power components in a design
• Understanding of the power-friendly features in the Microsemi IGLOO FPGA family
• Understanding of power analysis using Microsemi's SmartPower analysis tool
• Techniques to reduce power consumption in a design

Course Requirements:

• Basic understanding of the ProSIC3 FPGA architecture.
• Knowledge of the Libero SoC toolset and VHDL or Verilog

Designing with ProASIC3 is a 1-day class for engineers who are designing with Microsemi's ProASIC3-based FPGAs. This class describes the ProASIC3 FPGA architecture, including the logic tile, RAM blocks, clock conditioning circuitry, user FlashROM, and routing resources. This class will also introduce techniques on using the architectural features to improve design performance or area utilization. Hands-on lab exercises include performance analysis and the use of the special features available in this family. This course is offered at Microsemi's headquarters in San Jose, CA.

Course Objectives:

• Understanding of the ProASIC3 FPGA family architecture details including:
• Logic tile
• Memory blocks
• Clock conditioning circuitry
• User FlashROM
• Understanding of how to use architectural features in the ProASIC3 family to optimize designs for area or performance

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Designing with SmartFusion is a 2-day class for FPGA designers, embedded designers and firmware engineers who are designing with Microsemi's SmartFusion mixed signal FPGAs. This class describes the SmartFusion architecture, including SmartFusion microcontroller subsystem (MSS), analog compute engine (ACE) and FPGA fabric along with the software tools and design flows for implementing SmartFusion designs. Hands-on lab exercises targeting the SmartFusion Evaluation kit are included to provide practical applications of the material presented. This course is offered at Microsemi's headquarters in San Jose, CA

Course Objectives:

• Development with and understanding of the SmartFusion architecture details
• Development with and understand of the SmartFusion design flows to quickly implement SmartFusion applications

Students should have a basic understanding of the Microsemi ProASIC3 flash-based FPGA architecture. Students who are unfamiliar with ProASIC3 architecture should attend the Designing with ProASIC3 training class.

Course Requirements:

• Experience with PCs, Windows operating system, Microsemi Libero SoC toolset and software development tools, such as SoftConsole, Keil or IAR, are recommended.

Course Outline:

• Day 1: SmartFusion Microcontroller Subsystem
  (Intended for all engineers who are implementing SmartFusion designs)
  • SmartFusion MSS architecture
  • SmartFusion MSS I/Os
  • SmartDesign MSS configurator
  • Firmware drivers and sample projects for SoftConsole, Keil and IAR toolchains
  • Hands-on labs
• Day 2: SmartFusion FPGA Fabric Interface
  (Intended for engineers who want to implement logic in the SmartFusion FPGA fabric)
  • SmartFusion Analog front end and Analog Compute Engine (ACE)
  • SmartFusion FPGA fabric resources and fabric interface
  • SmartFusion digital I/Os
  • Adding user logic in SmartFusion designs
  • Microsemi Libero SoC design flow for SmartFusion
  • Hands-on labs

Introduction to Fusion is a 1-day class for engineers who are designing with Microsemi's Fusion mixed signal FPGA. This class describes the Fusion architecture, including Fusion Analog blocks, the Fusion bus interface, FlashROM and the software tools for implementing Fusion designs. Hands-on lab exercises include performance analysis and use of the special features available in this family. This course is offered at Microsemi's headquarters in San Jose, CA

Course Objectives:

• Understanding the Microsemi Fusion architecture details
• Understanding how to use architectural features in the Fusion family

Students should have a basic understanding of the Microsemi ProASIC3 flash-based FPGA architecture. Students who are not familiar with the ProASIC3 architecture should attend the Designing with ProASIC3 training class.

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Advanced Fusion Design is a 1-day class that builds on the concepts presented in the Introduction to Fusion training class. The course examines the Fusion mixed signal FPGA architecture in detail, including the NVRAM and Analog block along with the software tools to implement designs. Applications using the Fusion peripherals such as data logging, context switching, and power sequencing are introduced. Additional topics include Fusion soft IP, simulation of analog inputs, synthesis, and layout. Hands-on lab exercises are provided to reinforce the topics presented. This course is offered at Microsemi's headquarters in San Jose, CA

Course Objectives:

• Detailed understanding of the architectural features in the Fusion family
• Understanding of how to configure the Fusion peripherals
• Understanding simulation, synthesis, and layout
• Introduction to Fusion applications

Students should have a basic understanding of the Fusion architecture. Students who are not familiar with the Fusion architecture should attend the Introduction to Fusion training class.

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Suggested Prerequisite:

• Introduction to Fusion

Designing with RTAX-S/SL is a 1-day course that introduces the antifuse-based, HiRel RTAX-S/SL family. This class describes the specific features and architectural differences between the Microsemi Axcelerator FPGA family and the RTAX-S/SL family such as the EDAC RAM and local clocks. Techniques for improving design performance—both area and timing are also introduced. Hands-on lab exercises include performance analysis and use of the special features available in this family. This course is offered at Microsemi's headquarters in San Jose, CA

Students should be familiar with the Microsemi Axcelerator FPGA architecture or attend the Designing with Axcelerator training class.

Course Objectives:

• Understanding of the RTAX-S/SL FPGA family architecture details including logic modules, Memory Blocks, Clock Conditioning Circuitry and I/Os
• Understanding of how to use architectural features in the Axcelerator family to optimize designs for area or performance
• Understanding of performance analysis of special architectural features

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero IDE toolset

Designing with RTAX-DSP is a 1-day course offered at Microsemi's facility in San Jose, CA. The course introduces the RTAX-DSP space-flight FPGA family. This class describes the specific architectural features of the family including the embedded radiation-tolerant multiply-accumulate blocks which provide a dramatic increase in device performance and utilization when implementing arithmetic functions such as those encountered in DSP algorithms.

IP for implementing DSP functions and techniques for improving design performance are introduced. Hands-on lab exercises are included to reinforce the topics presented.

Course Objectives:

• Understanding of the RTAX-DSP FPGA family architecture details including logic modules, Memory Blocks, Math Blocks, Clock Conditioning Circuitry and I/Os
• Understanding of how to optimize design for utilization and performance

Course Requirements:

• Background in digital logic design
• Familiarity with DSP fundamentals and design
• Familiarity with Microsemi Libero IDE toolset
• Familiarity with Mathworks Matlab and Simulink are helpful, but not necessary

This 1-day course introduces Microsemi's SmartFusion cSoC as a solution for power and thermal management. The course material will introduce SmartFusion as a solution for thermal management and power management applications and introduce the SmartFusion Mixed Signal Power Manager (MPM) solution. Additional topics include customization of the MPM solution.

This course is offered at the Microsemi SoC Product Group headquarters in San Jose, CA. Students who cannot travel to San Jose can attend remotely.

Course Objectives:

• Understand the SmartFusion cSoC thermal and power management capabilities
• Understand the SmartFusion MPM solution and how to customize it for a specific application

Course Requirements:

• Basic understanding of the SmartFusion cSoC architecture.
• Familiarity with the Microsemi Libero SoC toolset and software development tools such as SoftConsole, Keil or IAR.

Introduction to CorePCIF is a 1-day course offered at Microsemi's facility in San Jose, CA. The course consists of presentation of PCI concepts and bus transactions, an introduction to the Microsemi CorePCIF module (with FIFO backend) and hands-on labs.

Course Objectives:

• Understanding of basic PCI concepts and bus transactions
• Understanding of the Microsemi CorePCIF module with a focus on how the back-end interface works
• Functional simulation, synthesis, layout, and timing analysis of the Microsemi CorePCIF module

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Advanced CorePCIF is a 1-day course offered at Microsemi's facility in San Jose, CA that builds on the Introduction to CorePCIF course and is intended for customers who have purchased the Microsemi CorePCIF (with FIFO backend) module. The course examines the Microsemi CorePCIF module architecture in detail and describes synthesis and layout of the cores. Students will look at strategies for area and timing optimization as well as the CorePCIF testbenches. Hands-on lab exercises are provided in simulation, timing optimization, and testbench modification.

Course Objectives:

• Understanding of the Microsemi CorePCIF (with FIFO back-end) module architecture
• Understanding functional simulation, synthesis, layout, and timing analysis of the CorePCIF module.
• Timing and area optimization of the CorePCIF module.
• Modification of the CorePCIF testbench.

Course Requirements:

• Experience with PCs, Windows operating system, and Microsemi Libero SoC toolset

Suggested Prerequisite:

• Introduction to CorePCIF