Axcelerator

Download the application notes below to find out how to use Actel Axcelerator FPGA devices in a specific application or process.

	AC288: Using LVDS for Actel's Axcelerator and RTAX-S/SL Devices App Note		2 MB	5/2012	Click on the to rate this document
	AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note  Library Files (ZIP, 1.62 KB, 3/12)		708 KB	3/2012	Click on the to rate this document
	AC373: Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note   Design Files (ZIP, 5.1 MB, 11/11)		2 MB	11/2011	Click on the to rate this document
	AC379: Advanced Static Timing Analysis Using SmartTime App Note		6 MB	11/2011	Click on the to rate this document
	AC225: Programming Antifuse Devices App Note		678 KB	11/2011	Click on the to rate this document
	AC354: Core8051s Debugging in Axcelerator and RTAX-S Device  Design Files (ZIP, 25.7 MB, 9/10)		1 MB	10/2011	Click on the to rate this document
	AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.2 and Newer EDAC Core from Libero IDE v7.2 (ZIP, 45 KB, 06/06)		691 KB	2/2008	Click on the to rate this document
	AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.1 and Older EDAC Core from Libero IDE v7.1 or Earlier (ZIP, 41KB, 07/04)		256 KB	7/2006	Click on the to rate this document
	AC249: I/O Features in Axcelerator Family Devices App Note  Relative Pin Locations (ZIP, 341 KB, 11/04)		1 MB	1/2006	Click on the to rate this document
	AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note		713 KB	8/2005	Click on the to rate this document
	AC218: Using Axcelerator RAM as Multipliers App Note		381 KB	2/2005	Click on the to rate this document
	AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note		232 KB	2/2005	Click on the to rate this document
	AC212: Designing a SuperClock with an Axcelerator Device App Note  Design File (ZIP, 130 KB, 09/04)		409 KB	9/2004	Click on the to rate this document
	AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note  Design File (ZIP, 1.2 MB, 07/04)		642 KB	7/2004	Click on the to rate this document
	AC210: Laser Range Finder Using Actel’s Axcelerator FPGA App Note  Design File (ZIP, 345 KB, 07/04)		1 MB	7/2004	Click on the to rate this document
	AC209: Axcelerator Family Footprint Compatibility App Note		44 KB	7/2004	Click on the to rate this document
	AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment App Note		80 KB	5/2004	Click on the to rate this document
	AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note		148 KB	8/2003	Click on the to rate this document
	AC183: Using Global Resources in Actel's Axcelerator Family App Note		123 KB	8/2003	Click on the to rate this document
	AC182: Axcelerator I/O Selection Guide App Note		362 KB	8/2003	Click on the to rate this document
	AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note  Source Code (ZIP, 12 KB, 07/04)		186 KB	7/2003	Click on the to rate this document
	AC175: Axcelerator Family PLL and Clock Management App Note		174 KB	6/2003	Click on the to rate this document
	AC173: Differences Between RTAX-S/SL and Axcelerator App Note		62 KB	5/2003	Click on the to rate this document
	AC170: Prototyping RTAX-S Using Axcelerator Devices App Note		131 KB	4/2003	Click on the to rate this document
	AC163: Axcelerator Carry-Connect Macros App Note		118 KB	1/2003	Click on the to rate this document
	AC164: Axcelerator Family Memory Blocks App Note		151 KB	1/2003	Click on the to rate this document